Principal AI Chip Design Engineer(SG)

Lead RTL design and implementation for AI chip SoC and subsystems. Own key modules such as AI accelerator control logic, DMA, NoC/interconnect, memory subsystem, die-to-die/chip-to-chip interfaces, register blocks, interrupt, clock/reset, and low-power control. Define microarchitecture, RTL partitioning, interfaces, and implementation plans. Translate architecture and microarchitecture specifications into clean, reusable, synthesizable RTL. Lead SoC/IP integration, bus/interconnect integration,…